The present invention relates to a family of working liquids useful in modifying exposed intermediate surfaces of structured wafers for semiconductor fabrication, to methods of modifying exposed intermediate surfaces of structured wafers for semiconductor fabrication utilizing such a family of working liquids, and to semiconductor wafers made according the foregoing process.
During integrated circuit manufacture, semiconductor wafers used in semiconductor fabrication typically undergo numerous processing steps, including deposition, patterning, and etching steps. Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff et al., "Abrasive Machining of Silicon", published in the Annals of the International Institution for Production Engineering Research, (Volume 39/2/1990), pp. 621-635. In each manufacturing step, it is often necessary or desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing steps.
In conventional semiconductor device fabrication schemes, a flat, base silicon wafer is subjected to a series of processing steps that deposit uniform layers of two or more discrete materials which together form a single layer of what will become a multilayer structure. In this process, it is common to apply a uniform layer of a first material to the wafer itself or to an existing layer of an intermediate construct by any of the means commonly employed in the art, to etch pits into or through that layer, and then to fill the pits with a second material. Alternatively, features of approximately uniform thickness comprising a first material may be deposited onto the wafer, or onto a previously fabricated layer of the wafer, usually through a mask, and then the regions adjacent to those features may be filled with a second material to complete the layer. Following the deposition step, the deposited material or layer on a wafer surface generally needs further processing before additional deposition or subsequent processing occurs. When completed, the outer surface is substantially globally planar and parallel to the base silicon wafer surface. A specific example of such a process is the metal Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric (e.g., silicon dioxide) layer. After etching, optional adhesion/barrier layers are deposited over the entire surface. Typical barrier layers may comprise tantalum, tantalum nitride, titanium nitride or titanium, for example. Next, a metal (e.g., copper) is deposited over or on top of the adhesion/barrier layers. The deposited metal layer is then modified, refined or finished by removing the deposited metal and regions of the adhesion/barrier layer on the surface of the dielectric. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface would reveal a planar surface with metal corresponding to the etched pattern and dielectric material adjacent to the metal. The metal(s) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different physical characteristics, such as different hardness values. The abrasive treatment used to modify a wafer produced by the Damascene process must be designed to simultaneously modify the metal and dielectric materials without scratching the surface of either material. The abrasive treatment must create a planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
Such a process of modifying the deposited metal layer until the oxide dielectric material is exposed on the wafer outer surface leaves little margin for error because of the submicron dimensions of the metal features located on the wafer surface. The removal rate of the deposited metal should be relatively fast to minimize manufacturing costs, and the metal must be completely removed from the areas that were not etched. The metal remaining in the etched areas must be limited to discrete areas or zones while being continuous within those areas or zones to ensure proper conductivity. In short, the metal modification process must be uniform, controlled, and reproducible on a submicron scale.
One conventional method of modifying or refining exposed surfaces of structured wafers employs methods that treat a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in a liquid. Typically this slurry is applied to a polishing pad and the wafer surface is then ground or moved against the pad in order to remove material from the wafer surface. Generally, the slurry may also contain chemical agents that react with the wafer surface. This type of process is commonly referred to as a chemical-mechanical planarization (CMP) process.
A recent alternative to CMP slurry methods uses an abrasive article to modify or refine a semiconductor surface and thereby eliminate the need for the foregoing slurries. This alternative CMP process is reported in International Publication No. WO 97/11484, published Mar. 27, 1997. The reported abrasive article has a textured abrasive surface which includes abrasive particles dispersed in a binder. In use, the abrasive article is contacted with a semiconductor wafer surface, often in the presence of a working liquid, with a motion adapted to modify a single layer of material on the wafer and provide a planar, uniform wafer surface. The working liquid is applied to the surface of the wafer to chemically modify or otherwise facilitate the removal of a material from the surface of the wafer under the action of the abrasive article.
Working liquids useful in the process described above, either in conjunction with the aforementioned slurries or the abrasive articles, are typically aqueous solutions of a variety of additives including complexing agents, oxidizing agents, passivating agents, surfactants, wetting agents, buffers, rust inhibitors, lubricants, soaps, or combinations of these additives. Additives may also include agents which are reactive with the second material, e.g., metal or metal alloy conductors on the wafer surface such as oxidizing, reducing, passivating, or complexing agents. Examples of such working liquids may be found, for example, in U.S. patent application Ser. No. 09/091,932 filed Jun. 24, 1998.
In the CMP processes mentioned above, dishing performance and removal rate are measurements of polishing performance. These performance measurements may depend on the use of the foregoing working liquids. Dishing is a measure of how much metal, such as copper, is removed from bond pads or wire traces below the plane of the intermediate wafer surface as defined by the difference in height between the copper and the tops of the barrier or dielectric layers following removal of the blanket copper or copper plus barrier layer. Removal rate refers to the amount of material removed per unit time. Removal rates greater than at least about 1000 .ANG. per minute are preferred. Lower removal rates, such as a few hundred angstroms per minute (.ANG./min) or less, are less desirable because they tend to create increases in the overall manufacturing costs associated with wafer manufacture.
It is desirable to provide improvements in chemical mechanical planarization by providing working liquids useful in modifying exposed intermediate surfaces of structured wafers for semiconductor fabrication and to methods of modifying the exposed intermediate surfaces of such wafers for semiconductor fabrication, preferably with improved, sustainable, metal removal rates and utilizing the foregoing family of working liquids. It is especially desirable to provide working liquids that are useful in the aforementioned methods and resulting in the fabrication of metal containing structured wafers with improved dishing characteristics.